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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. 6-channel, digital ground-level translator 19-5714; rev 1; 3/11 typical operating circuit general description the max14842 translates digital signals between two domains that have different ground references of up to 72v. the device features six communication channels, two bidirectional and four unidirectional. two of the four unidirectional channels go in each direction. the device is powered by two supply voltages that independently define the logic levels of each ground domain. the max14842 supports guaranteed data rates up to 30mbps on the four unidirectional channels and up to 2mbps on the two bidirectional channels. the bidirec - tional channels have open-drain outputs, making them suitable for i 2 c signals. i 2 c clock stretching and hot swapping is supported on the bidirectional channels. undervoltage lockout ensures that the output pins have a defined behavior during power-up, power-down, and during supply transients. for proper operation, ensure that 0v (v gndb - v gnda ) 72v. note that gndb must be greater than or equal to gnda. the max14842 is available in a 16-pin tqfn package and is specified over the -40 n c to +125 n c automotive temperature range. ordering information features s supports ground differences up to 72v s four unidirectional channels: two in/two out s two bidirectional channels s i 2 c compatible s supports i 2 c clock stretching s 30mbps unidirectional data rates s 2mbps bidirectional data rates s +3.3v to +5v level translation s undervoltage lockout s 4mm x 4mm, 16-pin tqfn package s -40 n c to +125 n c automotive temperature range applications telecommunication systems battery management i 2 c, smbus k , spi k , and microwire k signals medical systems power-over-ethernet ** ep = exposed pad. + denotes a lead(pb)-free/rohs-compliant package. smbus is a trademark of intel corp. spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corp. evaluation kit available ina1 0.1f5 v 3.3v outb1 ina2 outb2 outa1i nb1 outa2i nb2 i/oa1 r pua r pub v dda v ddb i/ob1 max14842 r pub v ddb i/ob2 i/oa2 for proper operation: 0v (v gndb - v gnda ) 72v gpio cs rst irq sda c scl r pua v dda wake addr uv alarm sda peripheral scl gnda gndb v dda v ddb v gg 0.1f part temp range pin-package MAX14842ATE+ -40 n c to +125 n c 16 tqfn-ep** max14842
6-channel, digital ground-level translator 2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dda to gnda ........................................................ -0.3v to +6v v ddb to gndb ........................................................ -0.3v to +6v gndb to gnda ..................................................... -0.3v to +80v ina1, ina2 to gnda .............................. -0.3v to (v dda + 0.3v) inb1, inb2 to gndb .............................. -0.3v to (v ddb + 0.3v) outa1, outa2 to gnda ...................... -0.3v to (v dda + 0.3v) outb1, outb2 to gndb ...................... -0.3v to (v ddb + 0.3v) i/oa1, i/oa2 to gnda ............................................ -0.3v to +6v i/ob1, i/ob2 to gndb ............................................ -0.3v to +6v common-mode transients (i.e., transients between gnda and gndb) ......................................... 10v/ f s short-circuit duration (outa1, outa2 to gnda; outb1, outb2 to gndb) ..................................... continuous continuous power dissipation (t a = +70 n c) tqfn (derate 25mw/ n c above +70 n c) ..................... 2000mw operating temperature range ........................ -40 n c to +125 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v dda - v gnda = +3.0v to +5.5v, v ddb - v gndb = +3.0v to +5.5v, v gndb - v gnda = 0 to +72v, t a = -40 n c to +125 n c, unless oth - erwise noted. typical values are at v dda - v gnda = +3.3v, v ddb - v gndb = +3.3v, v gndb - v gnda = +50v, t a = +25 n c.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . tqfn junction-to-ambient thermal characteristics ( q ja ) .... 40c/w junction-to-case thermal characteristics ( q jc ) ........... 6c/w package thermal characteristics (note 1) parameter symbol conditions min typ max unit dc characteristics supply voltage v dda relative to gnda 3.0 5.5 v v ddb relative to gndb 3.0 5.5 supply current i dda i ddb v dda - v gnda = +5.5v; v ddb - v gndb = +5.5v; v gndb - v gnda = +70v; all inputs at v gnda , v gndb , or +5.5v; no load 7.5 ma voltage between gndb and gnda v gg v gndb - v gnda 0 72 v side b leakage current i l 1 ma undervoltage-lockout threshold v uvlo v dda - v gnda , v ddb - v gndb 2 v undervoltage-lockout hysteresis v uvlohys v dda - v gnda , v ddb - v gndb 0.1 v logic inputs and outputs input logic threshold voltage v it i/oa1, i/oa2, relative to gnda 0.5 0.7 v input logic-high voltage v ih ina1, ina2, relative to gnda 0.7 x v dda v inb1, inb2, relative to gndb 0.7 x v ddb i/oa1, i/oa2, relative to gnda 0.7 i/ob1, i/ob2, relative to gndb 0.7 x v ddb max14842
6-channel, digital ground-level translator 3 electrical characteristics (continued) (v dda - v gnda = +3.0v to +5.5v, v ddb - v gndb = +3.0v to +5.5v, v gndb - v gnda = 0 to +72v, t a = -40 n c to +125 n c, unless oth - erwise noted. typical values are at v dda - v gnda = +3.3v, v ddb - v gndb = +3.3v, v gndb - v gnda = +50v, t a = +25 n c.) (note 2) parameter symbol conditions min typ max unit input logic-low voltage v il ina1, ina2, relative to gnda 0.8 v inb1, inb2, relative to gndb 0.8 i/oa1, i/oa2, relative to gnda 0.5 i/ob1, i/ob2, relative to gndb 0.3 x v ddb output logic-high voltage v oh outa1, outa2, relative to gnda, source current = 4ma v dda - 0.4v v outb1, outb2, relative to gndb, source current = 4ma v ddb - 0.4v output logic-low voltage v ol outa1, outa2, relative to gnda, sink current = 4ma 0.8 v outb1, outb2, relative to gndb, sink current = 4ma 0.8 i/oa1, i/oa2, relative to gnda, sink current = 10ma 0.6 0.9 i/oa1, i/oa2, relative to gnda, sink current = 0.5ma 0.6 0.85 i/ob1, i/ob2, relative to gndb, sink current = 30ma 0.4 input/output logic-low threshold difference d v tol i/oa1, i/oa2 (note 3) 50 mv input leakage current i l v ina1 , v ina2 , v dda = +3.6v, v inb1 ,v inb2 , v ddb = +3.6v -2 +2 f a v i/oa1 , v i/oa2 , v dda = +3.6v, v i/ob1 , v i/ob2 , v ddb = +3.6v -2 +2 input capacitance c in ina1, ina2, inb1, inb2, f = 1mhz (note 4) 4 pf dynamic switching characteristics maximum data rate dr max ina1 to outb1, ina2 to outb2, inb1 to outa1, inb2 to outa2 30 mbps i/oa1 to i/ob1, i/oa2 to i/ob2, i/ob1 to i/oa1, i/ob2 to i/oa2 2 minimum pulse width pw min ina1 to outb1, ina2 to outb2, inb1 to outa1, inb2 to outa2 30 ns propagation delay t dplh t dphl ina1 to outb1, ina2 to outb2, inb1 to outa1, inb2 to outa2, v dda = v ddb = +3.0v, r l = 1m i , c l = 15pf, figure 1 20 30 ns t dplh t dphl i/oa1 to i/ob1, i/oa2 to i/ob2, v dda = v ddb = +3.0v, r 1 = 1.6k i , r 2 = 180 i , c l1 = c l2 = 15pf, figure 2 30 100 t dplh t dphl i/ob1 to i/oa1, i/ob2 to i/oa2, v dda = v ddb = +3.0v, r 1 = 1k i , r 2 = 120 i , c l1 = c l2 = 15pf, figure 2 60 100 max14842
6-channel, digital ground-level translator 4 electrical characteristics (continued) (v dda - v gnda = +3.0v to +5.5v, v ddb - v gndb = +3.0v to +5.5v, v gndb - v gnda = 0 to +72v, t a = -40 n c to +125 n c, unless oth - erwise noted. typical values are at v dda - v gnda = +3.3v, v ddb - v gndb = +3.3v, v gndb - v gnda = +50v, t a = +25 n c.) (note 2) note 2: all units are production tested at t a = +25 n c. specifications over temperature are guaranteed by design. all voltages of side a are referenced to gnda; all voltages of side b are referenced to gndb, unless otherwise noted. note 3: d v tol = v ol - v il . this is the minimum difference between the output logic-low voltage and the input logic threshold for the same i/o pin. this ensures that the i/o channels are not latched low when any of the i/o inputs are driven low (see the bidirectional channels section). note 4: guaranteed by design; not production tested. parameter symbol conditions min typ max unit propagation delay skew |t dplh C t dphl | t dskew i/oa1 to i/ob1, i/oa2 to i/ob2, v dda = v ddb = +3.0v, r 1 = 1.6k i , r 2 = 180 i , c l1 = c l2 = 15pf, figure 2 3 6 ns i/ob1 to i/oa1, i/ob2 to i/oa2, v dda = v ddb = +3.0v, r 1 = 1k i , r 2 = 120 i , c l1 = c l2 = 15pf, figure 2 30 100 channel-to-channel skew t dskewcc outb1 to outb2 output skew, figure 1 3 6 ns outa1 to outa2 output skew, figure 1 3 6 i/ob1 to i/ob2 output low skew, figure 2 3 10 i/oa1 to i/oa2 output low skew, figure 2 3 10 rise time t r outb1, outb2, outa1, outa2, 10% to 90%, figure 1 5 ns fall time t f outb1, outb2, outa1, outa2, 90% to 10%, figure 1 5 ns i/oa1, i/oa2, 90% to 10%, v dda = v ddb = +3.0v, r 1 = 1.6k i , r 2 = 180 i , c l1 = c l2 = 15pf, figure 2 30 60 i/ob1, i/ob2, 90% to 10%, v dda = v ddb = +3.0v, r 1 = 1k i , r 2 = 120 i , c l1 = c l2 = 15pf, figure 2 3 6 max14842
6-channel, digital ground-level translator 5 test circuits/timing diagrams figure 1. test circuit (a) and timing diagram (b) for unidirectional testing 0.1f v ddb v dda test source ina_ outb_ max14842 gnda gndb v dda v ddb v gg c l r l 0.1f 50 v dda ina1, ina2 (a) (b) 1.5v 1.5v 1.5v 1.5v 90% 10% 1.5v t dphl t dskewcc t f t r t dplh outb1 outb2 v ddb v ddb gnda gndb gndb max14842
6-channel, digital ground-level translator 6 test circuits/timing diagrams (continued) figure 2. test circuit (a) and timing diagrams (b) and (c) for bidirectional testing 0.1f v ddb v dda test source i/oa_ i/ob_ max14842 gnda gndb v dda v ddb v gg c l2 c l1 0.1f r 2 r 1 v dda i/oa1, i/oa2 (a) (b) 1.5v 1.5v 1.5v 90% 1.5v 1.5v 10% 1.5v t dphl t dskewcc t f t dplh i/ob1 i/ob2 v ddb v ddb gnda v ol (min) v ol (min) v ddb i/ob1, i/ob2 (c) 1.5v 1.5v 1.5v 1.5v 90% 10% 1.5v t dphl t dskewcc t f t dplh i/oa1 i/oa2 v dda v dda gndb v ol (min) v ol (min) max14842
6-channel, digital ground-level translator 7 typical operating characteristics (v dda - v gnda = +3.3v, v ddb - v gndb = +3.3v, v gndb - v gnda = +50v, r pua = r pub = 2k i , c l = 15pf, see the typical operating circuit , t a = +25 n c, unless otherwise noted.) propagation delay vs. capacitive load max14842 toc09 c l (pf) propagation delay (ns) 90 80 60 70 30 40 50 20 2 4 6 8 10 12 14 16 18 0 10 100 low to high high to low ina_ to outb_ propagation delay vs. supply voltage max14842 toc08 v dda (v) propagation delay (ns) 5.0 4.5 4.0 3.5 2 4 6 8 10 12 0 3.0 5.5 v gndb - v gnda = 0v v gndb - v gnda = 50v v gndb - v gnda = 72v v dda = v ddb ina_ to outb_ high-to-low transition propagation delay vs. supply voltage max14842 toc07 v dda (v) propagation delay (ns) 5.0 4.5 4.0 3.5 2 4 6 8 10 12 0 3.0 5.5 v gndb - v gnda = 0v v gndb - v gnda = 50v v gndb - v gnda = 72v v dda = v ddb ina_ to outb_ low-to-high transition output-voltage high vs. source current max14842 toc06 source current (ma) v oh (v) 40 30 20 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 05 0 outb1 v dda = 5.0v v dda = 3.3v output-voltage high vs. source current max14842 toc05 source current (ma) v oh (v) 40 30 20 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 05 0 outa1 v dda = 5.0v v dda = 3.3v i ddb vs. data rate max14842 toc04 data rate (mbps) i ddb (ma) 10 1 0.1 1.5 2.0 2.5 3.0 3.5 4.0 1.0 0.01 100 switching input on i/oa1 switching input on i/ob1 switching input on ina1 switching input on inb1 i dda vs. data rate max14842 toc03 data rate (mbps) i dda (ma) 10 1 0.1 1.5 2.0 2.5 3.0 3.5 1.0 0.01 100 switching input on i/ob1 switching input on i/oa1 switching input on ina1 switching input on inb1 i ddb vs. v ddb max14842 toc02 v ddb (v) i ddb (ma) 5.0 4.5 3.5 4.0 1 2 3 4 6 5 7 8 0 3.0 5.5 t a = +125c t a = +25c t a = -40c i dda vs. v dda max14842 toc01 v dda (v) i dda (ma) 5.0 4.5 4.0 3.5 1 2 3 4 5 6 7 0 3.0 5.5 t a = +125c t a = +25c t a = -40c max14842
6-channel, digital ground-level translator 8 typical operating characteristics (continued) (v dda - v gnda = +3.3v, v ddb - v gndb = +3.3v, v gndb - v gnda = +50v, r pua = r pub = 2k i , c l = 15pf, see the typical operating circuit , t a = +25 n c, unless otherwise noted.) propagation delay vs. supply voltage max14842 toc15 v dda (v) propagation delay (ns) 5.0 4.5 4.0 3.5 4 8 12 16 20 0 3.0 5.5 v gndb - v gnda = 0v v gndb - v gnda = 50v v gndb - v gnda = 72v v dda = v ddb i/oa_ to i/ob_ low-to-high transition propagation delay vs. temperature max14842 toc14 t a (c) propagation delay (ns) 110 95 80 65 50 35 20 5 -10 -25 2 4 6 8 10 12 0 -40 125 low to high high to low inb_ to outa_ propagation delay vs. capacitive load max14842 toc13 c l (pf) propagation delay (ns) 80 90 70 60 50 40 30 20 2 4 6 8 10 12 14 0 10 100 low to high high to low inb_ to outa_ propagation delay vs. supply voltage max14842 toc12 v dda (v) propagation delay (ns) 5.0 4.5 4.0 3.5 1 2 3 4 5 6 7 8 9 10 0 3.0 5.5 v gndb - v gnda = 0v v gndb - v gnda = 50v v gndb - v gnda = 72v v dda = v ddb inb_ to outa_ high-to-low transition propagation delay vs. supply voltage max14842 toc11 v dda (v) propagation delay (ns) 5.0 4.5 4.0 3.5 1 2 3 4 5 6 7 8 9 10 0 3.0 5.5 v gndb - v gnda = 0v v gndb - v gnda = 50v v gndb - v gnda = 72v v dda = v ddb inb_ to outa_ low-to-high transition propagation delay vs. temperature max14842 toc10 t a (c) propagation delay (ns) 110 95 -25 -10 5 35 50 65 20 80 2 4 6 8 10 12 14 16 0 -40 125 low to high high to low ina_ to outb_ max14842
6-channel, digital ground-level translator 9 typical operating characteristics (continued) (v dda - v gnda = +3.3v, v ddb - v gndb = +3.3v, v gndb - v gnda = +50v, r pua = r pub = 2k i , c l = 15pf, see the typical operating circuit , t a = +25 n c, unless otherwise noted.) propagation delay vs. temperature max14842 toc20 t a (c) propagation delay (ns) 110 95 80 65 50 35 20 5 -10 -25 10 20 30 40 50 60 70 0 -40 125 low to high high to low i/ob_ to i/oa_ propagation delay vs. supply voltage max14842 toc19 v ddb (v) propagation delay (ns) 5.0 4.5 4.0 3.5 44 48 52 56 60 40 3.0 5.5 v gndb - v gnda = 0v v gndb - v gnda = 50v v gndb - v gnda = 72v v dda = v ddb i/ob_ to i/oa_ high-to-low transition propagation delay vs. supply voltage max14842 toc18 v ddb (v) propagation delay (ns) 5.0 4.5 4.0 3.5 3 6 9 12 15 0 3.0 5.5 v gndb - v gnda = 0v v gndb - v gnda = 50v v gndb - v gnda = 72v v dda = v ddb i/ob_ to i/oa_ low-to-high transition propagation delay vs. temperature max14842 toc17 t a (c) propagation delay (ns) 110 95 80 65 50 35 20 5 -10 -25 8 10 12 14 16 18 6 -40 125 low to high high to low i/oa_ to i/ob_ propagation delay vs. supply voltage max14842 toc16 v dda (v) propagation delay (ns) 5.0 4.5 4.0 3.5 4 8 12 16 20 0 3.0 5.5 v gndb - v gnda = 0v v gndb - v gnda = 50v v gndb - v gnda = 72v v dda = v ddb i/oa_ to i/ob_ high-to-low transition max14842
6-channel, digital ground-level translator 10 pin configuration pin description 15 16 14 13 6 5 7 outa1 i/oa1 8 ina2 inb1 i/ob1 outb2 12 v ddb 4 12 11 9 v dda ina1 i/ob2 gndb gnda i/oa2 *ep *connect exposed pad to gnda. + outa2 inb2 3 10 outb1 tqfn (4mm 4mm) top view max14842 pin name function voltage relative to 1 ina2 logic input 2 on side a. ina2 is translated to outb2. gnda 2 outa1 logic output 1 on side a. outa1 is a push-pull output. gnda 3 outa2 logic output 2 on side a. outa2 is a push-pull output. gnda 4 i/oa1 bidirectional input/output 1 on side a. i/oa1 is translated to/from i/ob1 and is an open- drain output. gnda 5 i/oa2 bidirectional input/output 2 on side a. i/oa2 is translated to/from i/ob2 and is an open- drain output. gnda 6 gnda ground reference for side a. v gnda must be v gndb . 7 gndb ground reference for side b. v gndb must be v gnda . 8 i/ob2 bidirectional input/output 2 on side b. i/ob2 is translated to/from i/oa2 and is an open- drain output. gndb 9 i/ob1 bidirectional input/output 1 on side b. i/ob1 is translated to/from i/oa1 and is an open- drain output. gndb 10 inb2 logic input 2 on side b. inb2 is translated to outa2. gndb 11 inb1 logic input 1 on side b. inb1 is translated to outa1. gndb 12 outb2 logic output 2 on side b. outb2 is a push-pull output. gndb 13 outb1 logic output 1 on side b. outb1 is a push-pull output. gndb 14 v ddb supply voltage of logic side b. bypass v ddb with a 0.1 f f ceramic capacitor to gndb. gndb 15 v dda supply voltage of logic side a. bypass v dda with a 0.1 f f ceramic capacitor to gnda. gnda 16 ina1 logic input 1 on side a. ina1 is translated to outb1. gnda ep exposed pad. connect ep to gnda. max14842
6-channel, digital ground-level translator 11 detailed description the max14842 provides both ground-level transla - tion and logic-level shifting needed in systems where there is a difference in ground references of up to 72v. the device is powered by two supply voltages, v dda and v ddb , which independently set the logic levels on either side of the device. v dda and v ddb are sepa - rately referenced to gnda and gndb, respectively. the max14842 supports data rates of up to 30mbps on each of the four unidirectional channels and 2mbps on the two bidirectional channels. ground translation/level shifting for proper operation, ensure that 0v p (v gndb - v gnda ) p 72v. note that gndb must be greater than or equal to gnda. also ensure that 3.0v p (v dda - v gnda ) p 5.5v and 3.0v p (v ddb - v gndb ) p 5.5v. (v dda - v gnda ) can be greater than or less than (v ddb - v gndb ), as long as each is within the normal operating range. unidirectional channels the device features four unidirectional channels that can each operate independently with a guaranteed data rate of up to 30mbps. the output driver of each unidirectional channel is push-pull, eliminating the need for pullup resistors. the drivers are also able to drive both ttl and cmos logic inputs. bidirectional channels the device features two bidirectional translation chan - nels that have open-drain outputs. the bidirectional channels do not require a direction input. a logic-low on one side causes the corresponding pin on the other side to be pulled low while avoiding data latching within the translator. to prevent latching of the bidirectional chan - nels, the input logic-low threshold (v it ) of i/oa1 and i/ oa2 is at least 50mv lower than the output logic-low volt - ages (v ol ) of i/oa1 and i/oa2. this prevents an output logic-low on side a from being accepted as an input low and subsequently transmitted to side b and vice versa. the i/oa1, i/oa2, i/ob1, and i/ob2 pins have open-drain outputs, requiring pullup resistors to their respective sup - plies for logic-high outputs. the output low voltages are guaranteed for sink currents of up to 30ma for side b and 10ma for side a (see the electrical characteristics table). the bidirectional channels of the device support i 2 c clock stretching. separate ground references the device is designed to translate logic signals to and from domains with isolated and offset ground references. startup and undervoltage lockout the v dda and v ddb supplies are both internally moni - tored for undervoltage conditions. undervoltage events can occur during power-up, power-down, or during normal operation due to a slump in the supplies. when an undervoltage event occurs on either of the supplies, all outputs on both sides are automatically controlled, regardless of the status of the inputs. the bidirectional outputs become high impedance and are pulled high by the external pullup resistor on the open-drain output. the unidirectional outputs are pulled high internally to the voltage of the v dda or v ddb supply during undervoltage conditions. functional diagram max14842 ina1 v dda v ddb gnda gndb ground reference shifter ina2 outa1 outa2 i/oa1 i/oa2 outb1 outb2 inb1 inb2 i/ob1 i/ob2 max14842
6-channel, digital ground-level translator 12 figure 3 shows the behavior of the outputs during power up and power down. applications information ac components on v gg when the ground difference voltage, v gg , has a time varying (ac) component, limit the amplitude to ensure that the max14842 operates as specified. the maximum allowable amplitude of an ac signal on v gg is a function of frequency. power-supply sequencing the max14842 does not require power-supply sequenc - ing. the logic levels are set independently on either side by v dda and v ddb . each supply can be present over the entire specified range regardless of the level or pres - ence of the other. power-supply decoupling to reduce ripple and the chance of introducing data errors, bypass v dda and v ddb with 0.1 f f ceramic capacitors to gnda and gndb, respectively. place the bypass capacitors as close to the power-supply input pins as possible. unidirectional and bidirectional level translator the max14842 operates both as a unidirectional device and bidirectional device simultaneously. each unidirec - tional channel can only be used in the direction shown in the functional diagram . the bidirectional channels function without requiring a direction input. chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. figure 3. undervoltage lockout behavior v dda v ddb outa1 outb1 package type package code outline no. land pattern no. 16 tqfn-ep t1644+4 21-0139 90-0070 max14842
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 13 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. 6-channel, digital ground-level translator revision history revision number revision date description pages changed 0 12/10 initial release 1 3/11 deleted the max14842ete+ from the ordering information , removed the future status from the MAX14842ATE+ in the ordering information , added the automotive temperature range to the features , absolute maximum ratings , and the electrical characteristics sections 1C4 max14842

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